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EN0-001 Questions and Answers
During an investigation into a software performance problem an engineer doubles the clock frequency of a cached ARM processor running the software. Unfortunately the performance of the application does not increase by very much, despite running on the processor for 100% of the time. What is likely to be the main bottleneck in the system?
The processor is context switching between multiple processes
Performance is limited by the speed of external memory
The processor is taking too long to execute branch instructions
The system is raising interrupts too fast for the processor to handle them
Which TWO of the following options are DISADVANTAGES of building source code to use software floating point? (Choose two)
Not all floating point arithmetic operations are supported
Floating point calculations have lower performance than hardware floating point
The stack cannot be used to pass floating point function arguments
The results of floating point calculations will be less accurate
The resulting code will be larger
Answer: B, E
A 32KB 4-way set associative instruction cache supports a cache line size of 64 bytes. How many bits are required to index a cache line in a way?
In a system using the Security Extensions, how does the Secure Monitor execute a switch from Secure to Non-secure state?
Encrypts Secure register contents, sets the NS bit in SCTLR and branches directly to Normal world code
Saves Secure register contents, sets all registers to zero, sets the NS bit in SCTLR and branches directly to Normal world code
Saves Secure register contents, loads Non-secure ones from memory, sets the NS bit in SCTLR and performs an exception return
Sets the NS bit in SCTLR and performs an exception return - all registers are banked in hardware and switched automatically
An ARM Cortex-A9 multi-core system has two CPUs, C1 and C2, each with a corresponding data cache. The code running on C1 writes to a memory location M. and C1 updates its data cache, but not main memory. After that, C2 tries to read the contents of memory location M. Which of the following hardware can automatically (without software inteivention) ensure that C2 reads the updated contents of M?
Snoop Control Unit
Tightly Coupled Memory
Level 2 Cache Controller
Dynamic Memory Access Controller
When should an ISB instruction be used?
When executing a long branch
When clearing the branch predictor caches
When reading a register from a coprocessor
Which of the following processors includes a Generic Interrupt Controller as a standard component?
Which of the following statements best describes a Board Support Package (BSP)?
PC interface hardware for configuring a boot monitor
Hardware specific source code needed for operating system support
A working port of Linux for a specific hardware platform
Debugging hardware and software supplied with a development board
What are the values of the NZCV bits in the CPSR after executing the following instructions?
LDR R0, = 0xFFFFFFFF ADDS R0, R0, #1
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